Serial

SPI

class openlabctrl.serial.spi.SPI(io, clk_div, cpol, cpha, sclk_mask=0b0001, cs_mask=0b0010, mosi_mask=0b0100, miso_mask=0b1000)

Bit-banged SPI master over a DigitalIo port.

Supports all four SPI modes (CPOL × CPHA) and configurable pin assignment via single-bit masks. Call io_config() once to initialize pin directions and idle states, then use cs_low(), write(), and cs_high() to drive a transaction.

Parameters:

• io (DigitalIo) – DigitalIo instance used for bit-banging.

• clk_div (int) – Clock divider relative to the frame clock. Must be a positive even integer ≥ 2. The SPI clock half-period is clk_div / 2 frame clock cycles.

• cpol (int) – Clock polarity. 0 = idle low, 1 = idle high.

• cpha (int) – Clock phase. 0 = data sampled on leading edge, 1 = on trailing edge.

• sclk_mask (int) – Single-bit mask selecting the SCLK pin.

• cs_mask (int) – Single-bit mask selecting the CS pin, active-low.

• mosi_mask (int) – Single-bit mask selecting the MOSI pin.

• miso_mask (int) – Single-bit mask selecting the MISO pin.

io_config()

Configure pin directions and set all SPI signals to their idle state.

Sets MISO as input and SCLK, CS, MOSI as outputs. SCLK is driven to its idle level (determined by cpol), CS is deasserted (high), and MOSI is driven low. Call this once before the first transaction.

cs_low(wait=1)

Assert chip select (drive CS low) and wait.

Parameters:

wait (int) – Number of half-clock periods to wait after asserting CS (actual delay = clk_div * wait frame clock cycles).

cs_high(wait=1)

Deassert chip select (drive CS high) after a settling delay.

Parameters:

wait (int) – Number of half-clock periods to wait before deasserting CS (actual delay = clk_div * wait frame clock cycles).

write(data, size)

Transmit size bits of data MSB-first over MOSI.

Clock edges follow the configured CPOL/CPHA mode. SCLK is returned to its idle level at the end of the transfer. CS must be asserted before calling this method (see cs_low()).

Parameters:

• data (int) – Integer value to transmit.

• size (int) – Number of bits to transmit (starting from the MSB).

UART

class openlabctrl.serial.uart.UART(io, baud, data_len=8, stop_len=1, parity=None, tx_mask=0b0001, rx_mask=0b0010)

Bit-banged UART transmitter over a DigitalIo port.

Transmits standard UART frames (start bit + data bits LSB-first + optional parity + stop bits). TX is implemented open-drain: the output register is pre-loaded to 0 and the pin is toggled between driven-low (tristate=0) and high-Z (tristate=1). The internal pull-up resistors on the DigitalIo ports keep both TX and RX lines idle-high (mark state) without requiring external pull-ups.

Parameters:

• io (DigitalIo) – DigitalIo instance used for bit-banging.

• baud (int) – Baud rate in bits per second. The bit period is derived from the IO clock frequency.

• data_len – Number of data bits per frame (default: 8).

• stop_len – Number of stop bits per frame (default: 1).

• parity – Parity mode. 0 = even, 1 = odd, None = no parity (default).

• tx_mask (int) – Single-bit mask selecting the TX pin.

• rx_mask (int) – Single-bit mask selecting the RX pin.

io_config()

Configure pin directions and pre-load the TX output register.

Sets both TX and RX to high-Z (idle/input mode) and pre-loads the TX output register to 0 so that driving TX low (start bit) is simply a matter of switching the pin to driven mode. Call this once before the first transmission.

write(data)

Transmit one or more bytes over TX.

Each byte is framed as: start bit (low), data_len data bits LSB-first, optional parity bit, and stop_len stop bits (high). Strings are UTF-8 encoded before transmission.

Parameters:

data (bytes | str) – Data to transmit. Accepts bytes or str.