Device

RP Base

class openlabctrl.device.rp_base.Rp_base(ip, label, daisy_0_en, daisy_1_en, force)[source]

Base class for Red Pitaya devices.

Parameters:
  • ip (str) – IP address or URL

  • label (str) – User-defined name

  • daisy_0_en (bool) – Enable daisy chain sync connector 0

  • daisy_1_en (bool) – Enable daisy chain sync connector 1

  • force (bool) – Force bitstream reloading (resets FPGA configuration)

get_uid()[source]

Return a unique device identifier of the form <label>@<ip>, e.g. my_rp@192.168.1.100.

Return type:

str

RP 125-14 Base

class openlabctrl.device.rp_125_14.Rp_125_14(ip, label, daisy_0_en, daisy_1_en, force)[source]

Bases: Rp_base

Base class for Red Pitaya STEMLab 125-14 devices (125 MHz, 14-bit ADC/DAC).

Parameters:
  • ip (str) – IP address or URL

  • label (str) – User-defined name

  • daisy_0_en (bool) – Enable daisy chain sync connector 0

  • daisy_1_en (bool) – Enable daisy chain sync connector 1

  • force (bool) – Force bitstream reloading (resets FPGA configuration)

CLK_FREQ = 125000000.0
IO_DICT
{
  "rf_out_0": {
    "class": RfOut,
    "addr": "0x0"
  },
  "rf_out_1": {
    "class": RfOut,
    "addr": "0x1"
  },
  "digital_io_0": {
    "class": DigitalIo,
    "addr": "0x4"
  },
  "digital_io_1": {
    "class": DigitalIo,
    "addr": "0x5"
  },
  "digital_io_2": {
    "class": DigitalIo,
    "addr": "0x6"
  },
  "digital_io_3": {
    "class": DigitalIo,
    "addr": "0x7"
  },
  "analog_out_0": {
    "class": AnalogOut,
    "addr": "0x8"
  },
  "analog_out_1": {
    "class": AnalogOut,
    "addr": "0x9"
  },
  "analog_out_2": {
    "class": AnalogOut,
    "addr": "0xa"
  },
  "analog_out_3": {
    "class": AnalogOut,
    "addr": "0xb"
  },
  "scope_0": {
    "class": Scope,
    "addr": "0xc"
  },
  "scope_1": {
    "class": Scope,
    "addr": "0xd"
  },
  "led": {
    "class": Led,
    "addr": "0xe"
  },
  "_sync": {
    "class": Sync,
    "addr": "0xf"
  }
}
get_uid()

See Rp_base.get_uid().

RP 125-14 Z7010

class openlabctrl.device.Rp_125_14_Z7010(ip, label='rp_125_14_z7010', daisy_0_en=False, daisy_1_en=False, force=False)[source]

Bases: Rp_125_14

Red Pitaya STEMLab 125-14 device class (Z7010 FPGA chipset):

  • STEMlab 125-14 (Gen 1)

  • STEMlab 125-14 Low Noise (Gen 1)

  • STEMlab 125-14 (Gen 2)

  • STEMlab 125-14 Pro (Gen 2)

Parameters:
  • ip (str) – IP address or URL

  • label (str) – User-defined name

  • daisy_0_en (bool) – Enable daisy chain sync connector 0

  • daisy_1_en (bool) – Enable daisy chain sync connector 1

  • force (bool) – Force bitstream reloading (resets FPGA configuration)

CLK_FREQ

See Rp_125_14.CLK_FREQ.

COMPATIBLE_DEVICES
[
  Rp_125_14_Z7020
]
IO_DICT

See Rp_125_14.IO_DICT.

get_uid()

See Rp_base.get_uid().

RP 125-14 Z7020

class openlabctrl.device.Rp_125_14_Z7020(ip, label='rp_125_14_z7020', daisy_0_en=False, daisy_1_en=False, force=False)[source]

Bases: Rp_125_14

Red Pitaya STEMLab 125-14 device class (Z7020 FPGA chipset):

  • STEMlab 125-14 Z7020 Low Noise (Gen 1)

  • STEMlab 125-14 Pro Z7020 (Gen 2)

Parameters:
  • ip (str) – IP address or URL

  • label (str) – User-defined name

  • daisy_0_en (bool) – Enable daisy chain sync connector 0

  • daisy_1_en (bool) – Enable daisy chain sync connector 1

  • force (bool) – Force bitstream reloading (resets FPGA configuration)

CLK_FREQ

See Rp_125_14.CLK_FREQ.

COMPATIBLE_DEVICES
[
  Rp_125_14_Z7010
]
IO_DICT

See Rp_125_14.IO_DICT.

get_uid()

See Rp_base.get_uid().